1. Field of the Invention
The invention relates generally to the semiconductor power devices. More particularly, this invention relates to configurations and methods for manufacturing of new and improved edge terminations for high voltage (HV) devices for improved reliability and to reduce the areas occupied by the termination areas while maintaining high breakdown voltages.
2. Description of the Prior Art
Conventional floating guard rings in the termination area are not reliable especially products housed in plastic packages due to spacing of the Floating Guard Rings (FGR) and the charge from dielectric layer under the metal layer, passivation film, and/or charge from the plastic molding compounds. Other high voltage (higher than 400V) termination structures, such as Junction Termination Extension GTE), Field Guard Ring and Field Plate (FGR-FP), minimize sensitivity of FGR type high voltage (HV) termination.
“Optimization and Surface Charge Sensitivity of High Voltage Blocking Structures with Shallow Junctions” by the inventor, Hamza Yilmaz, published in IEEE Transactions on Electron Devices, vol. 38, No. 3, July 1991, pp. 1666-167, discloses a high voltage blocking and termination structure using offset (optimum) multiple field plate and field-limiting ring (OFP-FLR) structure and optimized multiple zone JTE (MZ-JTE) structure to improve the breakdown voltage without additional passivation and process complexities. In the OFP-FLR structure, each field limiting ring has a field plate covering most of the surface space between two adjacent field limiting rings located at the surface of the silicon substrate with a gap between two field plates. A multiple zone JTE structure includes multiple lightly p-doped zones located at the surface of the silicon substrate and next to each other with the first p-JTE is next to the p+ electrode.
“Junction termination extension (JTE), A New Technique for Increasing Avalanche Breakdown Voltage and Controlling Surface Electric Fields in P-N Junctions” by Victor A. K. Temple, published in International Electron Devices Meeting, 1977, PP. 423-426, discloses a method of forming a junction termination extension to improve the breakdown voltage using implantation rather than by shaping or etching an already present semiconductor substrate. The advantages of this method are immediately apparent-control over the actual dopant charge to one percent accuracy and added flexibility in that the implant step can be done almost anywhere during processing.
U.S. Pat. No. 6,011,298 discloses a high voltage termination structure with buried field-shaping region for increasing a breakdown voltage. The termination structure includes a buried field-shaping region, such as a buried field-shaping ring, separated from and beneath the device region with a sufficient to permit a depletion region to form between the buried field-shaping shaping region and the device region when a first voltage is applied between the device region and the substrate and to produce a larger radius of curvature of the depletion region formed about the device region when a second voltage that is larger than the first voltage is applied between the device region and the substrate.
U.S. Pat. No. 4,158,206 discloses semiconductor device, which includes a body of semiconductor material having a PN junction terminating at a major surface, with buried field limiting rings formed within the body and extending around a portion of the PN junction. Buried field limiting rings reduce the electric field intensity at the surface intercept of the reverse biased PN junction, thus increase the reverse bias voltage sustainable by the PN junction of interest and increase the breakdown voltage of the semiconductor material.
However conventional FGR-FP does not completely shield surface of the HV termination region from charges from wafer surface passivation films and/or assembly and package material (i.e., molding compound and assembly site).
Therefore a need still exists to provide a termination configuration that completely seals the surface of the HV termination region with poly Silicon or metal gate MOSFET structures.